/*
 * cs1256.h
 *
 *  Created on: 2017-11-3
 *      Author: Administrator
 */

#ifndef __CS1259B_H_
#define __CS1259B_H_

#define     C_AFE_ADDR_SYS                  0x00
#define     C_AFE_ADDR_ADC0                 0x01
#define     C_AFE_ADDR_ADC1                 0x02
#define     C_AFE_ADDR_ADC2                 0x03
#define     C_AFE_ADDR_ADC3                 0x04
#define     C_AFE_ADDR_ADC4                 0x05
#define     C_AFE_ADDR_ADC5                 0x06
#define     C_AFE_ADDR_BIM0                 0x07
#define     C_AFE_ADDR_BIM1                 0x08
#define     C_AFE_ADDR_ADO                  0x09
#define     C_AFE_ADDR_ADS                  0x0A

#define     C_AFE_ADDR_CONFIG               0x10
#define     C_AFE_ADDR_VREFT                0x11
#define     C_AFE_ADDR_LDOT                 0x12
#define     C_AFE_ADDR_OSCT                 0x13
#define     C_AFE_ADDR_TST1                 0x14
#define     C_AFE_ADDR_TST2                 0x15
#define     C_AFE_ADDR_TMUX                 0x16
#define     C_AFE_ADDR_OTPCON               0x59
#define     C_AFE_ADDR_TEST                 0x5a

#define     C_AFE_DELAY	                    200         //@cpuclk=2MHz

// ;----------------------------------------------------------------------
// ; define register value
// ;----------------------------------------------------------------------
#define     C_AFE_SFR_ADC0_IR0			   0b11010010   //;- AIN3, + AIN2
#define     C_AFE_SFR_ADC0_IR1			   0b11001011   //;- AIN2, + AIN3

#define     C_AFE_SFR_ADC0_NTC			   0b11000000   //;- AIN1, + AIN0
// #define     C_AFE_SFR_ADC0_WEIGHT		   0xC0 //0b11000000   //;- AIN1, + AIN0
#define     C_AFE_SFR_ADC0_WEIGHT		   0xC0 //0b11000000   //;- AIN1, + AIN1
// ;Bit7	IMOD: Modulator MOD current control bit
// ;	0 = current in common mode
// ;	1 = current in high-performance mode = current in common mode x2*

// ;Bit6	FS_SEL: Sampling frequency selection bit
// ;	0 = 331.11KHz			
// ;	1 = 662.22KHz*

// ;Bit5-3	INNS[2:0]: PGA negative port input signal selection bit
// ;	111 = TSN			
// ;	110 = BIMN(when TMODE=11)
// ;	101 = 1/2 VS
// ;	100 = GND(when TMODE=10)
// ;   011 = AIN4
// ;   010 = AIN3*
// ;   001 = AIN2**
// ;   000 = AIN1***

// ;Bit2-0	INPS[2:0]: PGA positive port input signal selection bit
// ;	111 = TSP		
// ;	110 = BIMP(when TMODE=11)
// ;	101 = 1/2 VS
// ;	100 = 1/8 VDD(when TMODE=10)
// ;	011 = AIN3**
// ;   010 = AIN2*
// ;   001 = AIN1
// ;   000 = AIN0***

#define     C_AFE_SFR_ADC1_IR              0b01001110 
#define     C_AFE_SFR_ADC1_NTC             0b01000000//;0b00100000                   //;gain=1x1 
// #define     C_AFE_SFR_ADC1_WEIGHT          0x2E                                      //;20hz gain=32x4 
#define     C_AFE_SFR_ADC1_WEIGHT          0x4E                                      //;40hz gain=32x4 
// #define     C_AFE_SFR_ADC1_WEIGHT          0x4D                                      //;40hz gain=32x4 
// #define     C_AFE_SFR_ADC1_WEIGHT          0x6E                                      //;80hz gain=32x4 
// ;Bit7-5	DR[2:0]: ADC data rate selection bit
// ;	000 = 10Hz	
// ;	001 = 20Hz**	
// ;	010 = 40Hz*                                                         ;ir-mode dr=20hz
// ;	011 = 80Hz 	
// ;	100 = 160Hz
// ;	101 = 320Hz
// ;	110 = 640Hz	
// ;	111 = 1280Hz 

// ;Bit4	BUFBP: buffer control bit
// ;	0 = Enable the buffer*		
// ;	1 = Disable the buffer (currently unavailable)

// ;Bit3-2	PGA[1:0]: PGA gain selection bit
// ;	00 = Gain=1**
// ;	01 = Gain=1
// ;	10 = Gain=16
// ;	11 = Gain=32*

// ;Bit1-0	ADGN[1:0]: Modulator gain selection bit
// ;	00 = Gain=1**
// ;	01 = Gain=2
// ;	10 = Gain=4(DR goes to 1/2)*
// ;	11 = Gain=8(DR goes to 1/4)
#define     C_AFE_SFR_ADC3                 0x00//0b00000000 
// ;Bit7  GTCSL: Gain warm-up drift compensation thickness selection bit
// ; 	0 = fine adjustment, used to adjust warm-up drift of the chip		
// ; 	1 = coarse adjustment = fine adjustment x6, used to compensate warm-up drift of the sensor

// ;Bit6-4 GTC[2:0]: Gain warm-up drift compensation selection bit (CTCSL=0)
// ; 	111 = 15ppm/C	
// ; 	110 = 10ppm/C	
// ; 	101 = 5ppm/C
// ; 	100 = 0ppm/C	
// ; 	000 = 0ppm/C*
// ; 	001 = -5ppm/C
// ; 	010 = -10ppm/C	
// ; 	011 = -15ppm/C

// ;Bit3   LVSCP: Level shift module chopping enable bit (valid when LVSHIFT is set to 1)
// ; 	0 = Disable chopping
// ; 	1 = Enable chopping, Chopping frequency = Fs/128

// ;Bit2   LVSHIFT: Level shift module enable bit
// ; 	0 = Disable level shift
// ; 	1 = Enable level shift

// ;Bit1-0 N/A
#define     C_AFE_SFR_ADC4_IR              0b01000000   //;0b01001100
#define     C_AFE_SFR_ADC4_NTC             0b01000000                
#define     C_AFE_SFR_ADC4_WEIGHT          0x40//0b01000000                
// ;Bit7-6	CHOPM[1:0]: Instrument amplifier (IA) and modulator (MOD) chopping frequency control bit
// ;	00 = Disable chopping
// ;	01 = The chopping frequency of the IA is fs_clk/32 and the chopping frequency of the modulator is fs_clk/256
// ;	10 = The chopping frequency of the IA is fs_clk/32 and the chopping frequency of the modulator is fs_clk/128
// ;	11 = The chopping frequency of the IA is fs_clk/64 and the chopping frequency of the modulator is fs_clk/128

// ;Bit5-4	ACCU_NUM[1:0]: COMB data cumulative number selection in duty cycle mode
// ;	00 = 8
// ;	01 = 16
// ;	10 = 32
// ;	11 = 64

// ;Bit3-2	ADREFS[1:0]: ADC reference voltage selection bit
// ;	00 = positive reference = external REFP; negative reference = external REFN*
// ;	01 = positive reference = VREF, which is external connected to REFP, then it links back to ADC. Negative reference = external REFN
// ;	10 = positive reference = internal VREF; negative reference = GND
// ;	11 = positive reference = internal VREF; negative reference = GND	

// ;Bit1-0	LDOS[1:0]: Internal LDO output VS voltage selection bit
// ;	00 = 2.35V*
// ;	01 = 2.45V
// ;	10 = 2.8V
// ;	11 = 3.0V
#define     C_AFE_SFR_ADC5                 0x00//0b00000000   //;0b00010000 
// ;Bit7-5	N/A

// ;Bit4	EXFIL_EN: Enable bit for PGA input signal to connect an external filter
// ;   0 =  Not use an external RC filter
// ;   1 =  Use an external RC filter

// ;Bit3	REG_NC: Reserved bit

// ;Bit2	FIL_EN: Low-pass filter enable control signal after COMB
// ;	0 = Disable the filter			
// ;	1 = Enable the filter	

// ;Bit1	FIL_CON1: Filtering cascading control
// ;	0 = The filter uses the cascade structure		
// ;	1 = The filter does not use the cascade structure

// ;Bit0	FIL_CON2: Filter coefficient control
// ;	0 =  Use coefficient 1			
// ;	1 =  Use coefficient 2	
#define     C_AFE_SFR_SYS                  0x16//0x3E//0b00111110
// ;Bit7-6	TMODE[7:6]: Measurement mode control bit
// ;	00 = manual measurement mode*
// ;	01 = temp-sensor measurement mode
// ;	10 = volt measurement mode
// ;	11 = BIM measurement mode	

// ;Bit5-4	PMODE[1:0]: Working mode control bit (valid only when TMODE is set to 00)
// ;	00 = common mode (currently unavailable)
// ;	01 = high-performance mode
// ;	10 = duty cycle mode, DR=640Hz
// ;	11 = free mode*

// ;Bit3	ENREF: VREF module enable bit
// ;	0 = Disable VREF
// ;	1 = Enable VREF*

// ;Bit2	ENADC: ADC module enable bit
// ;	0 = Disable the ADC
// ;	1 = Enable the ADC*

// ;Bit1	ENLDO: LDO module enable bit
// ;	0 = Disable LDO
// ;	1 = Enable LDO*

// ;Bit0	N/A


//---------------------------------------------------------
void AFE_Rest_Communicate_Interface(void);
void AFE_ResetCmd(void);
bool AFE_ReadResetStatus(void);
unsigned char AFE_Reset(void);  
void AFE_Reset_Next(void);
void F_AFE_INIT(void);
void AFE_POWER_DOWN(void);
void AFE_ReadReg(unsigned char addr,unsigned char byte, unsigned char *p);
unsigned int AFE_ReadAdc(void);
void CS_RegisterADTrage(void);
void CS_unRegisterADTrage(void);
#endif /* CS1256_H_ */
